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HCC/HCF4031B
64-STAGE STATIC SHIFT REGISTER
.FULLYSTATI .STANDARD .RECI .THREECASCADI
.QUI .STANDARDI .5V,10V,AND15VPARAMETRI .I .100%TESTEDFORQUI .MEETSALLREQUI
DESCRIPTION
C OPERATION : DC to 16MHz (TYP.) @ VDD - VSS = 15V TTL DRIVE CAPABILITY ON Q OUTPUT RCULATION CAPABILITY NG MODES : DIRECT CLOCKING FOR HIGH-SPEED OPERATION DELAYED CLOCKING FOR REDUCED CLOCK DRIVE REQUIREMENTS ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS ESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE ZED, SYMMETRICAL OUTPUT CHARACTERISTICS C RATINGS NPUT CURRENT OF 100nA at 18V AND 25C FOR HCC DEVICE ESCENT CURRENT REMENTS OF JEDEC TENTATIVE STANDARD NO. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES"
EY (Plastic Package)
F (Ceramic Package)
C1 (Chip Carrier) ORDER CODES : HCC4031BF HCF4031BEY HCF4031BC1
PIN CONNECTIONS
The HCC4031B (extended temperature range) and HCF4031B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. The HCC/HCF4031B is a static shift register that contains 64 D-type, master-slave flip-flop stages and one stage which is a D-type master flip-flop only (referred to as a 1/2 stage). The logic level present at the DATA input is transferred into the first stage and shifted one stage at each positive-going clock transition. Maximum clock frequencies up to 16 Megahertz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. The HCC/HCF4031B has a MODE CONTROL input that, when in the high state, allows operation in the recirculating mode. The MODE CONTROL input can also be used to select between two separate data sources. Register packages can be cascaded and the clock lines driven directly for high-speed operation. Alternatively, a delayed clock output(CLD) is provided that enables cascading regJune 1989 1/12
HCC/HCF4031B
ister packages while allowing reduced clock drive fan-out and transition-time requirements. A third cascading option makes use of the Q' output from the 1/2 stage, which is available on the next negative-going transition of the clock after the Q output occurs. This delayed output, like the delayed clock CLD, is used with clocks having slow rise and fall times.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol V DD* VI II Pt ot Parameter Supply Voltage : HC C Types H C F Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range Operating Temperature : HCC Types H CF Types Storage Temperature Value - 0.5 to + 20 - 0.5 to + 18 - 0.5 to V DD + 0.5 10 200 100 - 55 to + 125 - 40 to + 85 - 65 to + 150 Unit V V V mA mW mW C C C
Top Tstg
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at theseor any other conditions abovethose indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol V DD VI T op Parameter Supply Voltage : HCC Types HC F Types Input Voltage Operating Temperature : H CC Types H C F Types Value 3 to + 18 3 to + 15 0 to V DD - 55 to + 125 - 40 to + 85 Unit V V V C C
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HCC/HCF4031B
LOGIC DIAGRAM AND TRUTH TABLES
INPUT CONTROL CIRCUIT
Data 1 0 X X Recirc. X X 1 0 Mode 0 0 1 1 Bit Into Stage 1 1 0 1 0
TYPICAL STAGE
Data 0 1 X
1 = HIGH LEVEL
OUTPUT FROM Q' (pin 5)
CL - -/ - -/ -\ - D ata + 1 0 1 NC
0 = LOW LEVEL X = DON'T CARE
Data + 6 4 0 1 X
CL -\ - -\ - - -/
NC = NO CHANGE
Data + 64.5 0 1 NC
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HCC/HCF4031B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Symbol IL Parameter Quiescent Current Test Conditions VO |I O | V D D VI (V) (V) (A) (V) 0/ 5 5 0/10 10 0/15 15 0/20 20 0/ 5 5 0/10 10 0/15 15 0/ 5 <1 5 0/10 <1 10 0/15 <1 15 5/0 <1 5 10/0 <1 10 15/0 <1 15 0.5/4.5 < 1 5 1/9 <1 10 1.5/13.5 < 1 15 4.5/0.5 < 1 5 9/1 <1 10 13.5/1.5 < 1 15 0/ 5 2.5 5 0/ 5 4.6 5 0/10 9.5 10 0/15 13.5 15 0/ 5 2.5 5 0/ 5 4.6 5 0/10 9.5 10 0/15 13.5 15 0/ 5 0.4 5 0/10 0.5 10 0/15 1.5 15 0/ 5 0.4 5 0/10 0.5 10 0/15 1.5 15 0/ 5 0.4 5 0/10 0.5 10 0/15 1.5 15 0/ 5 0.4 5 0/10 0.5 10 0/15 1.5 15 18 Any Input 15 Any Input 0.3 10 - 5 0.3 5 7.5 1 pF T L o w* Min. Max. 5 10 20 100 20 40 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -2 - 0.64 - 1.6 - 4.2 - 1.53 - 0.52 - 1.3 - 3.6 2.56 6.4 16.8 2.08 5.01 13.6 0.64 1.6 4.2 0.52 1.3 3.6 0.1 Value 25 C Min. Typ. Max. 0.04 5 0.04 10 0.04 20 0.08 100 0.04 20 0.04 40 0.04 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 - 1.6 - 3.2 - 0.51 - 1 - 1.3 - 2.6 - 3.4 - 6.8 - 1.36 - 3.2 - 0.44 - 1 - 1.1 - 2.6 - 3.0 - 6.8 2.04 4 5.2 10.4 13.6 27.2 1.74 4 4.42 10.4 11.56 27.2 0.51 1 1.3 2.6 3.4 6.8 0.44 1 1.1 2.6 3.0 6.8 10 - 5 0.1 T Hi g h * Min. Max. 150 300 600 3000 150 300 600 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 - 1.15 - 0.36 - 0.9 - 2.4 - 1.1 - 0.36 - 0.9 - 2.4 1.44 3.6 9.6 1.43 3.74 9.52 0.36 0.9 2.4 0.36 0.9 2.4 1 A Unit
HCC Types
A
HCF Types V OH Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Output Source Current (Source) Q, Q, Q CL D
V
V OL
V
V IH
V
V IL
V
I OH
HCC Types
mA
HCF Types
I OL
Output HCC Sink Current Q Types HCF Types
mA
I OL
Output Sink Current Q, Q' CL D Input Leakage Current
HCC Types HCF Types
mA
I IH , I IL
HCC 0/18 Types
CI
HCF 0/15 Types Input Capacitance
* TLow = - 55C for HCC device : - 40C for HCF device. * THigh = + 125C for HCC device : + 85C for HCF device. The Noise Margin for both "1" and "0" level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5 V min. with VDD = 15V.
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HCC/HCF4031B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25C, C L = 50pF, R L = 200k, typical temperature coefficient for all V DD values is 0.3%/C, all input rise and fall times = 20ns)
Symbol Parameter Test Conditions V D D (V) Min. 5 10 15 5 10 15 5 10 15 t THL ' , t T L H Transition Time : (any output, except Qt THL ) 5 10 15 t T HL Q, 5 10 15 tset up Data Setup Time 5 10 15 t h o ld Data Hold Time 5 10 15 tW Clock Pulse Width 5 10 15 f max Maximum Clock Input Frequency** 5 10 15 t r, t f Clock Input Rise or Fall Time* 5 10 15 2 5 6 Value Typ. 250 110 90 190 80 65 100 50 40 100 50 40 50 25 20 30 15 10 30 15 10 120 50 40 4 10 12 1000 1000 200 s MHz Max. 500 220 180 380 160 130 200 100 80 200 100 80 100 50 40 60 30 20 60 30 20 240 100 80 ns ns ns ns ns ns ns ns Unit
t P HL , Propagation Delay Time : t PL H, t PL H Clock to Q, Clock to Q t P HL , Propagation Delay Time : t PL H, t PHL Clock to Q' Clock to Q Clock to CL D
* If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the propagation delay at 50pF and the transmition time of the output driving stage. * * Maximum Clock Frequency for Cascaded Units; a) Using Delayed Clock Feature in Recirculation Mode : 1 fmax = where n = nimber of packages (n-1) CLD prop. delay + Q prop. delay + set-up time b) Not Usng Delaye Clock : 1 fmax = propagation delay + set-up time
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HCC/HCF4031B
Typical Output Low (sink) Current Characteristics. Minimum teristics. Output Low (sink) Current Charac-
Typical Output High (source) Current Characteristics.
Minimum Output High (source) Current Characteristics.
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HCC/HCF4031B
TYPICAL APPLICATIONS CASCADING USING DIRECT CLOCKING FOR HIGH SPEED OPERATION (SEE CLOCK RISE AND FALL TIME REQUIREMENT).
CASCADING USING DELAYED CLOCKING FOR REDUCED CLOCK DRIVE REQUIREMENTS.
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HCC/HCF4031B
TYPICAL APPLICATIONS (continued) CASCADING USING HALF- CLOCK-PULSE DELAYED DATA OUTPUT (Q') TO PERMIT USE OF SLOW RISE AND FALL TIME CLOCK INPUTS.
TEST CIRCUITS Quiescent Device Current. Noise Immunity.
Input Leakage Current.
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HCC/HCF4031B
Plastic DIP16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
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HCC/HCF4031B
Ceramic DIP16/1 MECHANICAL DATA
mm MIN. A B D E e3 F G H L M N P Q 7.8 2.29 0.4 1.17 0.22 0.51 0.38 17.78 2.79 0.55 1.52 0.31 1.27 10.3 8.05 5.08 0.307 0.090 0.016 0.046 0.009 0.020 3.3 0.015 0.700 0.110 0.022 0.060 0.012 0.050 0.406 0.317 0.200 TYP. MAX. 20 7 0.130 MIN. inch TYP. MAX. 0.787 0.276
DIM.
P053D
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HCC/HCF4031B
PLCC20 MECHANICAL DATA
mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180
DIM.
P027A
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HCC/HCF4031B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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